Classroom Glossary Public page

Week 1: Boolean Logic in Verilog

900 words

You built NAND gates from relays in Week 2 of CSA-101. This week you build the same gates in Verilog and wire them into the ALU module that every subsequent week builds on. The concept is identical; the medium is text instead of a drag-drop schematic; the reward is that Verilog synthesizes to a 32-bit chip.

Reading

  • Petzold weave anchors. Ch 4 (Anatomy of a Flashlight, p. 22), Ch 6 (relay and repeater, p. 44), Ch 11 (Gates, p. 129, De Morgan equivalences). About 30 pages total. You read these in CSA-101; re-read Ch 11 with attention to the De Morgan equivalences, which you will use to verify your Verilog module outputs against the truth tables from Week 2 of CSA-101.
  • Cross-chapter handout. handouts/cross-chapter-petzold-reading-guide.md (bookmark; used every week).

Lecture

3 hours. Key arc:

The transition from 6502-land to RV32I-Lite-land. In CSA-101 you built a 6502 by reading and modifying Arlet's existing Verilog. In CSA-110 you build the CPU from a blank module file, describing each gate explicitly. The 6502 is 3,500 NAND-equivalent gates in two files (cpu.v, alu.v). The RV32I-Lite CPU you build by Week 5 is about 1,400 NAND-equivalent gates in six files: alu.v, regfile.v, decoder.v, cpu.v, mem.v, top.v. Smaller because the instruction set is more regular; larger per gate because every data path is 32 bits instead of 8.

Verilog primitives review. module, input, output, wire, assign, always, posedge. The difference between combinational assign (used this week) and sequential always @(posedge clk) (used next week). Students who built a 6502 from Arlet's core will recognize every construct from Week 7 of CSA-101; the review is brief.

NAND universality in Verilog. Write a NAND gate: assign out = ~(a & b);. Build NOT, AND, OR, XOR from NAND by combining. Synthesize and verify against truth-table testbench. Identical structural exercise to CSA-101 Week 2 Labs 1.2 and 1.3; the difference is that you type the Verilog rather than dragging modules in the visual simulator.

Forward pointer. The ALU you wire this week has a 1-bit data path. Week 2 expands it to 32 bits. Week 5 integrates the ALU into the full CPU. The Verilog file structure you start now persists to the capstone.

Lab exercises

Four labs in labs/lab-1.md. Plan for ~5 hours.

  • Lab 1.1. Write nand.v, not.v, and.v, or.v, xor.v using only NAND primitives. Verify each against an iverilog truth-table testbench. This is the CSA-101 Week 2 exercise translated to Verilog text.
  • Lab 1.2. Wire NOT, AND, OR, XOR from your NAND primitive. No new primitives. Run the 4-input exhaustive testbench (lab1_gate_tb.v).
  • Lab 1.3. Write mux2.v (2-to-1 multiplexer from NAND) and demux2.v. Verify. The multiplexer is the first compound gate; the ALU uses it for operation selection.
  • Lab 1.4. Write half_adder.v from NAND. Verify sum and carry against all four input combinations. Forward pointer: next week you cascade two half adders into a full adder and then 32 full adders into the ripple-carry chain.

Independent practice

  • Re-read Petzold Ch 11 with attention to De Morgan's laws. Write the two equivalences in your Toolchain Diary entry for this week.
  • Synthesize one of your gate modules to a Tang Primer 25K bitstream (optional at this stage; confirms the toolchain chain works end-to-end before the labs get heavier in Week 5).
  • Start your Toolchain Diary entry for Week 1. New tools this week: iverilog, vvp (simulation runner), your IDE or text editor configured for Verilog syntax highlighting. If you used iverilog in CSA-101, note the shared entry and add any new observations specific to structural-only Verilog.

Architecture comparison sidebar

NAND universality: 6502 vs RV32I-Lite. The 6502's NAND gates and the RV32I-Lite's NAND gates are physically the same CMOS cells. What differs is how many of them are needed and how they are arranged.

The 6502 has one 8-bit ALU that handles addition, subtraction, AND, OR, XOR, shift, and compare. Its data path is 8 bits wide throughout. The RV32I-Lite ALU you are building is 32 bits wide on every path. A 32-bit full adder requires 32 full-adder stages to the 6502's 8, roughly four times the NAND count for the adder chain alone.

The 6502's complexity budget goes into addressing logic (13 modes, each requiring address computation circuitry) and the control PLA (programmable logic array that decodes variable-length opcodes). The RV32I-Lite spends that complexity budget on wider data paths and a larger register file. Neither is universally better; they are different design points on the same tradeoff curve.

Reflection prompts

  1. In CSA-101 you modified Arlet's existing Verilog to confirm you understood it. In CSA-110 you write the Verilog from a blank file. What does this change about the engineering process and the kind of bugs you encounter?
  2. Petzold spent several chapters arriving at NAND universality through historical relay circuits. You arrived at the same place in one week. What did Petzold's slow climb give the reader that this compressed version did not?
  3. Your NAND gate in Verilog is a single assign statement. Arlet's 6502 NAND equivalent is a CMOS cell in a foundry-specified library. At what point in the toolchain do these two representations converge into the same silicon?

What's next

Week 2 takes the half adder you built in Lab 1.4 and grows it into a 32-bit ripple-carry adder, then wires in subtraction and bitwise operations to form the full ALU. The 6502 equivalent is the ALU that took ~1,000 Verilog lines in Arlet's alu.v; the RV32I-Lite ALU is simpler at each operation because the operations are more orthogonal.