Lab 3: Memory — Register File and RAM

Week: 3
Points: 20
Time: ~5 hours
Deliverable: verilog/mem/ directory + waveform screenshots + diary/week-03.md

What you ship

• verilog/mem/dff.v — D flip-flop
• verilog/mem/regfile.v — 8-register file (x0-x7, x0 hardwired zero)
• verilog/mem/mem.v — byte-addressable memory (word + byte + halfword access)
• lab3_waveform.png — GTKWave screenshot showing Lab 3.1's clock-edge capture
• lab3_testbench_output.txt
• diary/week-03.md

Lab 3.1: D flip-flop and waveform capture

Write dff.v with synchronous reset and write-enable:

module dff #(parameter WIDTH = 1) (
    input             clk, reset, we,
    input  [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
);
    always @(posedge clk)
        if (reset)      q <= 0;
        else if (we)    q <= d;
endmodule

Run lab3_dff_tb.v which applies a clock for 16 cycles, toggling d at specific cycles. Capture the waveform with GTKWave. In your screenshot, annotate the setup-time window: mark the period before the clock edge where d must be stable.

Note: if you are using the browser-only path, use the academy workbench's built-in waveform viewer and export a screenshot.

Lab 3.2: Register file

Write regfile.v per the lecture template. Requirements:

• 8 registers (x0 through x7), each 32 bits wide
• x0 is hardwired to 0: reads always return 0; writes to x0 are silently ignored
• Two asynchronous read ports (rs1, rs2)
• One synchronous write port (rd) with write enable

Run lab3_regfile_tb.v:

1. Write values 1-7 to registers x1-x7
2. Read all 8 registers (including x0) and verify: x0 = 0, x1 = 1, ..., x7 = 7
3. Write 99 to x0; verify x0 still reads as 0
4. Simultaneously write x3=100 and read x3; verify the read returns the OLD value (not 100), since the write is synchronous but the read is asynchronous

Lab 3.3: Byte-addressable memory

Write mem.v supporting word, halfword, and byte accesses. The size input selects the access width:

Use UHW and UB (unsigned halfword, unsigned byte) variants with zero-extension for the LBU/LHU instructions. Add a sign_extend input.

Run lab3_mem_tb.v: write and read back at all three granularities, including endianness checks (RV32I is little-endian).

Lab 3.4: Metastability drill

Using your Lab 3.1 waveform:

1. Identify the clock period (time between rising edges)
2. Identify the setup time: how early before the rising edge must d be stable?
3. Answer in diary/week-03.md: what would happen to the flip-flop's output q if d changed exactly at the clock edge (within the setup window)? This is the metastability condition. Name one real-world circuit that deals with metastability and how.

Toolchain Diary

Record in diary/week-03.md:

• GTKWave setup if new to you (carry-forward from CSA-101 is fine with a note)
• The result of the simultaneous read-write test in Lab 3.2
• Your answer to the metastability question

Grading