If you completed CSA-101 and CSA-102, you already have most of this. The new installs are the RISC-V cross-compiler toolchain and the Ghidra update. The Tang Primer 25K you already own is the same board.
Hardware
You already have (from CSA-101):
- Sipeed Tang Primer 25K FPGA development board
- openFPGALoader or equivalent programmer
- Micro-USB or USB-C cable
- UART terminal (minicom or picocom) configured and working
New for CSA-110 (Weeks 11-14):
- VCP peripheral module (from the Virtus Peripheral IP Pack; same kit as CSA-101 full kit)
- Tang Primer 25K expansion header breakout (if not already ordered)
Browser-only path: No new hardware needed. The academy workbench supports every CSA-110 lab except the final flash-to-silicon step.
Software: New Installs
RISC-V cross-compiler toolchain (required, Week 4 onward)
# Ubuntu / Debian
sudo apt-get install gcc-riscv64-linux-gnu binutils-riscv64-linux-gnu
# macOS (Homebrew)
brew tap riscv-software-src/riscv
brew install riscv-tools
# Verify
riscv64-linux-gnu-as --version
riscv64-linux-gnu-objdump --version
# Expected: GNU assembler / objdump with riscv64-linux-gnu build
# The cross-assembler is 64-bit but we use RV32I mode:
riscv64-linux-gnu-as -march=rv32i -mabi=ilp32 test.s -o test.o
Ghidra (required, Week 4 onward)
If you used Ghidra in CSA-101 or SPK-101, update to the latest version (10.3 or later is preferred). CSA-110 uses the RISC-V processor module which ships with Ghidra 10.3+.
# Download from https://ghidra-sre.org/
# Or via package manager:
# sudo apt-get install ghidra (Ubuntu 24.04+)
# Verify RISC-V support:
# In Ghidra: New Project → Import File → select an RV32I binary
# Processor: RISC-V:LE:32:RV32I
Python 3 (already have from CSA-102)
CSA-110 reuses Python for:
- The two-pass assembler (Weeks 6-7)
- The VM translator (Weeks 8-9)
- The compiler (Weeks 10-12)
No new Python packages are required. If you're starting fresh:
# Verify Python 3.10+ is available
python3 --version
# Expected: Python 3.10.x or later
Software: Carry-Forward from CSA-101
These should already be working. Verify before Week 1:
# Gowin/Apicula toolchain (from CSA-101)
yosys --version # expected: Yosys 0.35 or later
nextpnr-himbaechel --version # expected: nextpnr-himbaechel 0.7 or later
gowin_pack --version # optional; can use openFPGALoader directly
# FPGA programmer
openFPGALoader --version
# Iverilog for simulation
iverilog -V # expected: Icarus Verilog version 12 or later
# UART terminal
minicom --version # or picocom --version
Student Repository Setup
# Clone the CSA-110 student template
git clone https://git.virtuscyberacademy.org/students/csa110-template.git csa110
cd csa110
# Directory structure:
# verilog/ -- Verilog source for your RV32I-Lite CPU (Weeks 1-5)
# toolchain/ -- Assembler, linker, VM translator, compiler (Weeks 6-12)
# os/ -- Virtus OS services (Weeks 13-14)
# capstone/ -- Capstone program source + binary + write-up (Week 14)
# diary/ -- Toolchain diary (week-by-week)
# Toolchain Diary template
cp diary/TEMPLATE-toolchain-diary.md diary/toolchain-diary.md
Verification Checklist
Run before Week 1 lab:
# 1. RISC-V cross-tools
riscv64-linux-gnu-as -march=rv32i -mabi=ilp32 /dev/null -o /dev/null 2>&1 && echo "AS OK"
riscv64-linux-gnu-objdump --version > /dev/null && echo "OBJDUMP OK"
# 2. Iverilog simulation
echo "module test; initial begin \$display(\"OK\"); \$finish; end endmodule" > /tmp/test.v
iverilog /tmp/test.v -o /tmp/test && /tmp/test && echo "IVERILOG OK"
# 3. openFPGALoader detects the Tang Primer 25K
openFPGALoader --detect 2>&1 | grep -i "tang\|gowin\|gw5a" && echo "FPGA DETECTED" || echo "FPGA not found (use browser path)"
# 4. Python 3
python3 -c "print('PYTHON OK')"
All four lines should print OK before the first lab session. If openFPGALoader does not detect the board, use the browser-only path until the hardware is available.