You built a 6502 on an FPGA. You wrote the toolchain that targets it. CSA-110 runs the same arc again, but the chip is a 32-bit RISC you design from scratch, the toolchain targets RV32I-Lite, and the operating system you write at the end runs on silicon you synthesized yourself. Every week is "you already know this concept from the 6502; here is how it works four registers and 24 bits wider."
Course mission and audience
CSA-110 is the 32-bit RISC arc of the academy's computer systems sequence. Students who have taken CSA-101 and CSA-102 arrive with a working 6502 on a Tang Primer 25K and a compiler toolchain that targets it. CSA-110 rebuilds every layer of that stack on RV32I-Lite: a 32-bit instruction set derived from the RISC-V specification, designed to be learnable in a single semester without sacrificing real-world relevance.
The audience is CSA-101 + CSA-102 graduates. A student who has not taken CSA-101 and CSA-102 will need 20-30 additional hours in the first three weeks; every week file notes the specific prior-knowledge that matters and what to read if you lack it.
Position in the pipeline. Belt 4/5. Bridge between the 6502 pair (CSA-101 + CSA-102) and the advanced architecture course (CSA-201). CSA-110 graduates gate into CSA-201, CON-101, and RE-101.
Why CSA-110 after CSA-101 + CSA-102? The 6502 is historically grounded, small, and irregular: 13 addressing modes, 3 accumulator-class registers, 8-bit data path, 16-bit address space. RV32I-Lite is clean, regular, and modern: 4 instruction formats, 32-bit data path, 32 registers, 32-bit address space. A student who has built both knows why RISC won the architectural debate of the 1980s and 1990s, not as an assertion but as a felt engineering difference.
What you will know at the end
In Bloom's-taxonomy order:
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Remember. Recite the RV32I-Lite instruction set (11 instructions plus 8 pseudo-instructions, 4 formats, 8 registers). Name the seven stages of the toolchain: source code to tokens to parse tree to VM bytecode to assembly to object file to linked binary. State the Virtus OS standard-library service roster (9 primary services plus 2 helpers).
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Understand (hardware). Explain the difference between an 8-bit and 32-bit register file at the gate level. Explain why RV32I's fixed 32-bit instruction width simplifies the decoder compared to the 6502's variable-length encoding. Explain how a three-register instruction format (rd, rs1, rs2) enables the compiler to keep more values in registers instead of spilling to memory.
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Understand (toolchain). Explain why the RV32I-Lite assembler needs two passes (symbol collection, then encoding) while your CSA-102 assembler could get away with one pass on most 6502 code. Explain what a static linker does that the 6502's flat-address model did not require. Explain why a stack-based VM maps cleanly to a register-based ISA.
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Apply (hardware). Implement the full RV32I-Lite data path in Verilog: 32-bit ALU, 8-register file, instruction decoder, fetch-decode-execute cycle. Synthesize to a Tang Primer 25K bitstream. Flash and run a hand-encoded binary.
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Apply (toolchain). Write a working two-pass assembler, a static linker, a VM translator, a compiler front end (tokenizer + recursive-descent parser), and a compiler back end (code generator). Build Virtus OS: Math, Memory, Output, Screen, and the other standard-library services.
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Analyze (cross-layer). Trace one source-code line through every stage of your toolchain: source character to token to parse-tree node to VM op to assembly mnemonic to encoded 32-bit word to bus transaction on your simulated CPU. Do the same trace for the 6502 toolchain you built in CSA-102 and note exactly where the two paths diverge and why.
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Create (capstone). Deliver a working Virtus Console: your own RV32I-Lite CPU on Tang Primer 25K silicon; your VCP integration via the IP Pack; a Virtus OS program that uses standard-library services; a 60-90 second demo video; a write-up. Same destination as the original CSA-101; you get there faster because of what you already know.
Course shape (14 weeks)
| Week | Theme | Petzold weave anchor | Architecture comparison sidebar | Lab focus |
|---|---|---|---|---|
| 1 | Boolean Logic in Verilog | Ch 4 + Ch 6 + Ch 11 | NAND universality: 6502 gates vs RV32I-Lite gates; same physics, different encoding width | 32-bit ALU module: NAND-only primitives in Verilog |
| 2 | Boolean Arithmetic: 32-bit | Ch 12 + Ch 13 | 8-bit ripple carry (CSA-101) vs 32-bit ripple carry; why the 6502's BCD mode disappears in RV32I-Lite | 32-bit ripple adder + ALU + IEEE-754 hand encoding |
| 3 | Memory: Registers and RAM | Ch 14 + Ch 16 | 6502's 3-register file vs RV32I-Lite's 8-register file (CSA-201 expands to 32) | D flip-flop + 8-register file + byte-addressable RAM in Verilog |
| 4 | Machine Language: RV32I-Lite ISA | Ch 17 + Ch 19 | 6502: variable-length, 13 addressing modes; RV32I-Lite: fixed 32-bit, 4 formats; why the RISC discipline reduced encoding complexity | Hand-encode 10 instructions + hand-decode 10 words + sum-to-N + Ghidra |
| 5 | Computer Architecture: CPU Integration | Ch 17 + Ch 18 | 6502 single-cycle (CSA-101 Arlet core) vs RV32I-Lite single-cycle; future pipeline (CSA-201 deferred) vs 6502's no-pipeline-ever | Instruction decoder + CPU integration + synthesize to Tang Primer 25K + first boot |
| 6 | Assembler | Ch 17 + Ch 24 | VOF v1 vs 6502 flat binary; why the RV32I-Lite assembler needs two passes when most 6502 code fits in one | Two-pass tokenizer + pass-2 encoder + VOF emit + sum-to-N round-trip |
| 7 | Static Linker | Ch 17 + Ch 22 + Ch 24 | Static linking vs the flat-address model Py6502v used; what a symbol table is and why flat 6502 could skip it | Symbol resolution + relocation + link two files + boot on silicon |
| 8 | VM I: Stack Arithmetic | Ch 17 + Ch 22 + Ch 24 | Stack VM vs the register-direct model 6502 compilers prefer; why RV32I-Lite makes stack lowering cheaper | Stack-arithmetic translator + memory-segment translator + end-to-end on silicon |
| 9 | VM II: Function Calls | Ch 17 + Ch 22 + Ch 25 | Calling conventions: RV32I-Lite Virtus vs 6502's JSR + stack-pull convention + ARM AAPCS | Program-flow translator + function-call protocol + recursive factorial on silicon |
| 10 | Compiler I: Syntax Analysis | Ch 24 + Ch 25 | Recursive descent vs the hand-written Py6502v parser in CSA-102; what changes at 32-bit | Tokenizer + recursive-descent parser + full parser + round-trip |
| 11 | Compiler II: Code Generation | Ch 22 + Ch 24 + Ch 25 | Treewalk codegen vs the SSA-IR LLVM uses; why your Py6502v codegen and this one share the same structural decision | Symbol table + codegen + subroutines + end-to-end on silicon + Ghidra on your own output |
| 12 | Compiler III: OS-Aware Compilation | Ch 22 + Ch 24 + Ch 25 | Hosted vs freestanding: Py6502v targeted the 6502 runtime; VirtusLang targets Virtus OS stdlib | Library-call codegen + multi-file compilation + end-to-end on Virtus Console HDMI |
| 13 | Virtus OS | Ch 22 (final) + Ch 25 (final) | Virtus OS stdlib vs POSIX vs 6502's minimal runtime from CSA-102 vs Win32 | Math + Memory/String/Array + Screen + Keyboard + VCP integration |
| 14 | Capstone delivery | Closing reflection on the full ladder | The bridge talk: where RV32I-Lite leads next (CSA-201, CON-101, RE-101) | Integration + demo video + write-up |
Anchor readings
Primary. Petzold, CODE: The Hidden Language of Computer Hardware and Software, 1st edition (1999). Same reading guide as the original CSA-101 pathway. Chapters 4, 6, 11, 12, 13, 14, 16, 17, 22, 24, 25. ~60 pages total. The Petzold weave columns above give the week-by-week allocation.
Secondary. Nisan and Schocken, The Elements of Computing Systems (the nand2tetris book). The course's structural model for Chapters 1-12. Students who want a parallel reading should pair each CSA-110 chapter with the corresponding nand2tetris chapter.
Tertiary. Patterson and Hennessy, Computer Organization and Design: RISC-V Edition. For students who want the full RV32I specification alongside the CSA-110 subset. Read in CSA-201, not CSA-110; CSA-110 covers only the RV32I-Lite teaching subset.
Reference. Waterman and Asanovic, The RISC-V Instruction Set Manual, Volume I (open access). Use to verify instruction encodings during lab exercises. The CSA-110 encoding card at handouts/cross-chapter-rv32i-lite-encoding-card.md is a curated extraction of the manual for the teaching subset.
Per-week time budget
| Activity | Hours per week | Hours over 14 weeks |
|---|---|---|
| Lecture | ~3 hr | ~42 hr |
| Lab (hands-on with Tang Primer 25K or workbench) | ~5 hr | ~70 hr |
| Independent practice (Petzold reading + repo work + Toolchain Diary entries) | ~3 hr | ~42 hr |
| Total | ~11 hr/week | ~155 hr |
Students arriving from CSA-101 + CSA-102 typically move 15-20% faster through Weeks 1-5 because the HDL workflow and the toolchain concept are already familiar. Budget the saved time in Weeks 10-13 (compiler and OS weeks), where the VirtusLang details are new regardless of background.
Equipment
Canonical. Sipeed Tang Primer 25K FPGA development board. GW5A-LV25 silicon. Carry forward from CSA-101. Same board; new bitstream.
Tier-1 alternative. Sipeed Tang Nano 20K. Same as CSA-101 advanced-track path.
Browser-only path. The academy workbench at https://virtuscyberacademy.org/workbench/ supports the full pipeline without hardware. Capstone requires either a kit or shared-bench access.
Full equipment and install details: SETUP.md.
Toolchain Diary
CSA-110 introduces ~30 new practitioner tools across 14 weeks (about 10 of these overlap with CSA-102 tools already known; Toolchain Diary entries for shared tools note the CSA-102 encounter and record the RV32I-specific difference). Each lab worksheet names the tools it introduces. The Toolchain Diary lives at ~/student-repo/toolchain-diary.md.
Key new tools introduced in CSA-110 that CSA-102 did not cover:
riscv64-linux-gnu-objdump(and related binutils) for RV32I-Lite disassemblyriscv32-unknown-elf-asfor assembler cross-check- The VOF v1 object file format and the static linker chain
- Ghidra for disassembling your own compiler output (returns from Week 4 every two weeks through Week 11)
Capstone (Week 14)
The Virtus Console build. Same end-state as the original CSA-101 capstone. Full specification: CAPSTONE.md.
What feeds into CSA-110
- CSA-101 (required): you arrive with a 6502 on a Tang Primer 25K and fluency in HDL + FPGA synthesis. Week 1 of CSA-110 immediately reuses these skills.
- CSA-102 (required): you arrive with a complete 6502 toolchain (assembler + Py6502v compiler + runtime library). CSA-110 builds the RV32I-Lite equivalent.
- FND-101 + FND-102: strongly recommended but technically covered by CSA-101 + CSA-102.
What CSA-110 feeds
- CSA-201 picks up where Week 14 ends: full RV32I (47 instructions), M extension, privileged ISA, MMU, PMP, compiler improvements, driver track.
- CON-101 uses the Virtus Console build as the target for a full retro-game development course.
- RE-101 uses the hardware instinct from Week 5 and the bit-level encoding fluency from Week 4 to reverse-engineer real hardware targets.
Outline v0.1 prepared 2026-05-30. Updates after the first pilot cohort.