Lab 1: Boolean Logic in Verilog

Week: 1
Points: 20 (graded with lab report)
Time: ~5 hours
Deliverable: verilog/gates/ directory in your student repo + diary/week-01.md

What you ship

• verilog/gates/nand.v — 1-bit NAND gate
• verilog/gates/not.v — NOT from NAND
• verilog/gates/and.v — AND from NAND
• verilog/gates/or.v — OR from NAND
• verilog/gates/xor.v — XOR from NAND
• verilog/gates/mux2.v — 2-to-1 multiplexer from NAND
• verilog/gates/demux2.v — 1-to-2 demultiplexer from NAND
• verilog/gates/half_adder.v — half adder from NAND
• lab1_testbench_output.txt — iverilog simulation output showing all tests pass
• diary/week-01.md — Toolchain Diary entry (see template)

Lab 1.1: NAND gate and derived gates

Write a 1-bit NAND gate using only the ~ and & Verilog operators:

// nand.v
module nand_gate(input a, input b, output out);
    assign out = ~(a & b);
endmodule

Write NOT, AND, OR, XOR using only nand_gate instances. No ~, &, |, ^ operators in the derived-gate files.

Run the truth-table testbench:

iverilog -o lab1_gates verilog/gates/nand.v verilog/gates/not.v \
    verilog/gates/and.v verilog/gates/or.v verilog/gates/xor.v \
    worksheets/csa-110/lab1_gates_tb.v
vvp lab1_gates > lab1_testbench_output.txt

All four truth tables should print with a PASS line per gate.

Lab 1.2: Verification against De Morgan's laws

Verify OR(a,b) == NOT(NAND(NOT(a), NOT(b))) using your gate modules. Write a 10-line Verilog test that exercises all four input combinations and checks equality. Include the output in your testbench output file.

Lab 1.3: Multiplexer

Write mux2.v (2-to-1 mux) from NAND. Symbol: mux2(input sel, input a, input b, output out). When sel=0, out=a; when sel=1, out=b. The mux requires 4 NAND gates. Verify against all 8 input combinations.

Write demux2.v (1-to-2 demux) from NAND. The demux routes a single input to one of two outputs based on the select signal. Verify.

Lab 1.4: Half adder

Write half_adder.v: sum = a XOR b, carry = a AND b. Use your xor.v and and.v modules (which in turn use only NAND). Verify all 4 input combinations:

Toolchain Diary entry

diary/week-01.md should record:

• New tools used: iverilog, vvp, gtkwave (if you used waveform viewing)
• If you used iverilog in CSA-101: note the shared entry and add any new observations about structural Verilog vs behavioral Verilog
• One specific thing that surprised you (expected or unexpected simulation behavior)
• Time spent on each lab section

Grading