Classroom Glossary Public page

Lab 4: Machine Language — Hand Encoding and Ghidra

451 words

Week: 4
Points: 25
Time: ~6 hours
Deliverable: asm/week-04/ directory + Ghidra session screenshot + diary/week-04.md


What you ship

  • asm/week-04/encode-10.md — hand-encoding worksheet (10 instructions with bit-field work)
  • asm/week-04/decode-10.md — hand-decoding worksheet (10 hex words → mnemonics)
  • asm/week-04/sum-to-n.s — sum-to-N assembly program
  • asm/week-04/sum-to-n-hand.hex — your hand-assembled hex
  • asm/week-04/sum-to-n-as.hex — assembler-produced hex (from riscv64-linux-gnu-as)
  • asm/week-04/ghidra-session.png — Ghidra screenshot showing RISC-V disassembly
  • diary/week-04.md

Lab 4.1: Hand-encode 10 instructions

Encode each instruction into a 32-bit hex word. Show the bit-field breakdown for each.

# Instruction Expected hex
1 ADD x3, x1, x2
2 SUB x4, x3, x1
3 ADDI x5, x0, 15
4 ADDI x6, x0, -1
5 LW x7, 8(x2)
6 SW x3, 4(x0)
7 BEQ x1, x2, +8 (offset = +8 bytes = 2 instructions ahead)
8 BNE x3, x0, -12 (offset = -12 bytes)
9 JAL x1, +20 (jump forward 20 bytes, save PC+4 to x1)
10 JALR x0, x1, 0 (return: jump to address in x1 + 0)

For each instruction, show: opcode bits, format type, register field values, immediate encoding. Show the final 32-bit binary and hex. Verify with:

riscv64-linux-gnu-as -march=rv32i -mabi=ilp32 encode-10.s -o encode-10.o
riscv64-linux-gnu-objdump -d encode-10.o

Lab 4.2: Hand-decode 10 hex words

Decode these 32-bit hex words into RV32I-Lite mnemonics. Show your work (which bits identify the format, which identify the opcode, register numbers, immediate).

0x00C58533
0x40208533
0xFFF00413
0x0002A283
0x00312023
0xFE209CE3
0x00108663
0x012181E3
0x00000013
0x00008067

For each word: identify the format (R/I/S/B/J), extract all fields, write the mnemonic with register names and immediate.

Verify with riscv64-linux-gnu-objdump.


Lab 4.3: Sum-to-N assembly program

Write sum-to-n.s in RV32I-Lite assembly. The program must:

  1. Load N = 10 into a register
  2. Initialize sum = 0 and loop counter i = 1
  3. Loop: sum += i; i++; if (i <= N) repeat
  4. Store the result at memory address 0
  5. End with an infinite loop (or EBREAK for simulation halt)

After writing the source, hand-assemble each instruction to a hex word. Record in sum-to-n-hand.hex as one 8-digit hex word per line.


Lab 4.4: Assembler round-trip

Assemble sum-to-n.s with riscv64-linux-gnu-as:

riscv64-linux-gnu-as -march=rv32i -mabi=ilp32 asm/week-04/sum-to-n.s -o sum-to-n.o
riscv64-linux-gnu-objdump -d sum-to-n.o
# Extract text section as hex:
riscv64-linux-gnu-objdump -j .text -s sum-to-n.o | grep '^ ' | awk '{print $2,$3,$4,$5}' | \
    tr ' ' '\n' | head -$(wc -l < sum-to-n-hand.hex) > sum-to-n-as.hex
diff sum-to-n-hand.hex sum-to-n-as.hex

If the diff is non-empty, find the discrepancy and explain it in your diary. Common causes: sign-extension of immediate, B-type offset encoding, pseudo-instruction expansion.


Lab 4.5: Ghidra first encounter (or second encounter)

Load sum-to-n.o into Ghidra. If you used Ghidra in CSA-101 or SPK-101 on 6502 binaries, this is the second encounter. If not, this is the first.

Steps:

  1. New project → Import file → sum-to-n.o
  2. Processor: RISC-V:LE:32:RV32I
  3. Analyze (default options)
  4. Screenshot the Listing window showing the disassembly

In your diary, answer: does Ghidra's disassembly match the source you wrote? If you used Ghidra on 6502 binaries in CSA-101, note one difference in the disassembly experience.


Toolchain Diary

Record in diary/week-04.md:

  • riscv64-linux-gnu-as version and installation path
  • riscv64-linux-gnu-objdump version
  • Ghidra version and the RISC-V processor module name
  • Any discrepancies found in Lab 4.4 and their explanations
  • Comparison to 6502 assembly encoding from CSA-101 (one paragraph)

Grading

Component Points
Hand-encoding: 10 instructions with bit-field work shown; verified against assembler 8
Hand-decoding: 10 hex words correctly identified with field extraction shown 5
Sum-to-N assembly program runs correctly (verified in simulation or on silicon) 7
Ghidra session screenshot showing RISC-V disassembly 3
Toolchain Diary entry with assembler discrepancy analysis 2