The hardware from weeks 1-3 meets the instruction set from week 4. By the end of the week you have a working RV32I-Lite CPU synthesized to a Tang Primer 25K bitstream, the bitstream flashed to silicon, and a sum-to-N program (the one you hand-wrote in week 4) executing on the CPU you designed.
This is the silicon bring-up week. It is the highest-friction week in CSA-101. Plan for unexpected hours.
Reading
- Chapter prose (primary). draft-chapters/ch5-computer-architecture-prose.md
- Petzold weave anchors. Ch 17 Automation (returning visit, pp. 209 + 212; the operator-leaves-the-room thesis); Ch 18 From Abaci to Chips (the historical lineage briefly). ~30 pages
- Cross-chapter handouts. FPGA cell to silicon bridge; RV32I-Lite encoding card (back on the desk)
Lecture
lectures/ch5-computer-architecture-lecture.md. 3 hours. Key arc:
- Fetch-decode-execute. The three stages every CPU runs continuously
- The instruction decoder. Opcode bits drive control signals; control signals route data through the ALU and register file
- Datapath vs control path. Separation of "what flows" from "what decides where it flows"
- Single-cycle vs multi-cycle. RV32I-Lite is single-cycle for teaching clarity; real CPUs pipeline (covered in CSA-201)
- The synthesis-to-silicon pipeline: Verilog → Yosys → nextpnr-himbaechel → Apicula gowin_pack → openFPGALoader → silicon
Figure 5.1. The control state machine your RV32I-Lite CPU steps through once per clock edge. Lab 5.1 builds the DECODE block; Lab 5.2 wires DECODE into the surrounding FETCH / EXECUTE / WRITEBACK stages and confirms the cycle closes. The sidebar notes name the control signals each state drives high. Single-cycle means all four states happen inside one clock period in the synthesized design, but the conceptual machine still walks them in order.
Lab exercises
Seven labs in worksheets/ch5/. The most consequential week of labs in the course.
- lab-5.1-instruction-decoder.md
- lab-5.2-cpu-integration-simulation.md, verify in simulation BEFORE you try to flash (GTKWave hand-trace; Tier-2)
- lab-5.2.5-step-through-visualizer.md, calibrate against the Workbench Tab 4 visualizer (Tier-1 companion to 5.2; pure-browser; the 5.2.5 numbering slots it between 5.2 and 5.3)
- lab-5.3-synthesize-tang-nano.md, the first flash; expect friction (Tier-2)
- lab-5.4-first-virtus-console-program.md, the moment your hardware runs your software
- lab-5.5-debug-seeded-failure.md, instructor-seeded bug; you debug it; the skill carries forward
- lab-5.6-reading-your-own-hardware.md
Plan for ~6 hours of lab (the visualizer companion adds ~75 minutes on top of the original budget). Add 2-3 hours of buffer for the silicon bring-up. Browser-path students stay in the workbench through the visualizer worksheet and skip the silicon-flash labs (5.3-synthesize and 5.4).
Independent practice
- Read Petzold Ch 17 carefully. This is the second of six visits to Ch 17. The chapter is the spine of the curriculum
- Update your Toolchain Diary. Week 5 introduces: Yosys synthesis, nextpnr-himbaechel place-and-route, Apicula gowin_pack bitstream generation, openFPGALoader flash, the academy workbench Tab 3 (browser path)
- Stretch: read the RISC-V User-Level ISA Specification §2 (Base Integer Instructions). Full RV32I is what CSA-201 extends to
Architecture comparison sidebar
RV32I-Lite is single-cycle. ARMv8 is out-of-order superscalar with multiple execution units. The 6502 historical anchor (Apple II, Commodore 64, NES, BBC Micro, Atari 2600) ran fetch-decode-execute in 2-7 clock cycles per instruction depending on addressing mode. Your single-cycle RV32I-Lite is faster per cycle than the 6502 ever was; it is dozens of times slower than a modern ARMv8 core. Same fetch-decode-execute pattern; different points on the engineering trade-off curve.
Reflection prompts
- Single-cycle CPUs are simple. Pipelined CPUs are fast. Why did the course start with single-cycle?
- The instruction decoder is essentially a giant lookup table from opcode bits to control signals. Why isn't the entire CPU just one big lookup table?
- The moment your hardware ran your software was probably memorable. Describe what you saw and how you felt. (The chapter prose calls this the "rest of the ladder you knew about" moment.)
What's next
Week 6 starts the toolchain. You wrote sum-to-N by hand in week 4 and ran it on silicon in week 5. Now you write the tool that translates from assembly mnemonics to encoded words: the assembler. The first software you write that produces software.