Scale the adder. Six worksheets in worksheets/ch2/ take you from the 4-bit ripple from week 1 to the terminal ALU (32-bit; adds; subtracts; logical ops) plus IEEE-754 hand encoding.
Anchors the week
Week 2: Boolean Arithmetic. The terminal ALU (lab 2.3) is the deliverable; the integer ALU you keep using through week 5 silicon bring-up. Floating-point (labs 2.4 + 2.5) is paper-and-pencil and software-only this week; the ALU does not need to do float.
Concept the lab embodies
Composition. The 32-bit adder is eight 4-bit adders chained. The adder-subtractor is one 32-bit adder plus 32 XOR gates plus one select bit. The terminal ALU is the adder-subtractor plus a multiplexer to pick between arithmetic and logical results. Same primitive parts; richer behavior through arrangement.
The six worksheets
| Worksheet | Time | Purpose |
|---|---|---|
| lab-2.0-discrete-adder-buildup.md | ~90 min | Discrete-IC adder buildup |
| lab-2.1-32bit-ripple-carry-adder.md | ~90 min | The scale-up |
| lab-2.2-adder-subtractor.md | ~60 min | Two's complement in hardware |
| lab-2.3-terminal-alu.md | ~90 min | The full ALU |
| lab-2.4-ieee754-hand-encoding.md | ~90 min | Paper-and-pencil float encoding |
| lab-2.5-software-fp-add.md | ~90 min | Software floating-point verifies your encoding |
Grading rubric
Per-worksheet rubrics inline. Week-level: ALU simulates correctly on at least one test bench; IEEE-754 encoding matches the IEEE specification for at least 4 chosen values; reflection journaled.
What's next
Lab pack 3: Memory. Sequential circuits enter; the flip-flop is the gateway.