The academy's flagship hardware-FPGA course. Students build a working RV32I-Lite CPU on a Tang Primer 25K FPGA, write its assembler, write its static linker, write its VM translator, write its compiler, and write Virtus OS on top. By the capstone, the student has personally produced every layer of the stack from logic gates to operating system.
Course mission and audience
CSA-101 is the academy flagship. It is the course that the entire pipeline orients around: students who finish CSA-101 own the complete computing stack, end to end, from Boolean gates to high-level language. Every downstream course (CSA-201 advanced architecture; RE-101 hardware reverse engineering; CON-101 console build; ADV-101 adversarial techniques) assumes CSA-101 graduates.
The audience is students who have finished FND-101 (digital foundations) and ideally HW-101 (hardware lab bench). Pre-CSA-101 students arrive with: number-base fluency; basic boolean logic; familiarity with bench instruments; basic Python comfort.
Position in the pipeline. Belt 4/5. Flagship. Gates CSA-201 + CON-101 + RE-101 hardware-CPU prerequisites. Direct prerequisite for the academy's three most demanding downstream tracks.
What you will know at the end
In Bloom's-taxonomy order:
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Remember. Recite the RV32I-Lite instruction set (11 instructions plus 8 pseudo-instructions, 4 instruction formats, 8 registers). Name the seven stages of the toolchain: source code → tokens → parse tree → VM bytecode → assembly → object file → linked binary. State the Virtus OS standard-library service roster (9 primary services plus 2 helpers).
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Understand (hardware). Explain how a flip-flop holds a bit; how a register file combines flip-flops with address decoders; how an ALU combines adder and subtractor with a select line; how an instruction decoder routes opcode bits to control signals; how the fetch-decode-execute cycle composes those pieces into a CPU.
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Understand (toolchain). Explain why the toolchain is multi-stage (separation of concerns; testability of each layer); explain what a symbol is in an object file and why static linking exists; explain why stack-based VMs translate cleanly to register-based machine code; explain why high-level languages need a parser, a code generator, and a runtime.
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Apply (hardware). Implement a 4-bit ripple adder in Verilog, simulate it, and synthesize to a Tang Primer 25K bitstream. Extend through a 32-bit ALU, a register file, an instruction decoder, and the full RV32I-Lite CPU. Flash the bitstream to silicon; run hand-encoded binaries.
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Apply (toolchain). Write a working two-pass assembler that consumes RV32I-Lite assembly, emits VOF object files, and produces flat binaries via your own linker. Write a VM translator that emits assembly. Write a compiler frontend that tokenizes and parses Jack-like syntax. Write a compiler backend that emits VM bytecode.
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Analyze (cross-layer). Trace one source-code line through every stage of your own toolchain: source character → token → parse-tree node → VM op → assembly mnemonic → encoded 32-bit word → bus transaction in your simulated CPU → flip-flop state.
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Create (capstone). Deliver a working Virtus Console: your own RV32I-Lite CPU on Tang Primer 25K silicon; your VCP integration via the IP Pack; a Virtus OS program running on top that uses standard-library services; a 60-90 second demo video; a write-up.
Course shape (14 weeks)
| Week | Theme | Chapter prose | Lab focus | Petzold weave anchor | Architecture comparison sidebar |
|---|---|---|---|---|---|
| 1 | Boolean Logic | Ch 1 | Discrete-logic breadboard + NAND-only gates | Petzold Ch 4 + Ch 6 + Ch 11 | NAND-universality across all silicon |
| 2 | Boolean Arithmetic | Ch 2 | 32-bit ripple adder + ALU + IEEE-754 hand encoding | Petzold Ch 12 + Ch 13 | RV32I-Lite ALU vs x86_64 AGU vs ARM NEON |
| 3 | Memory | Ch 3 | D-flip-flop metastability + register file + byte-addressable RAM | Petzold Ch 14 + Ch 16 | RV32I-Lite 8-register file vs full RV32I 32-register vs x86_64 16-register |
| 4 | Machine Language | Ch 4 | Hand-encode 10 instructions + decode 10 words + sum-to-N + Ghidra first encounter | Petzold Ch 17 + Ch 19 | RV32I-Lite 11 ops vs full RV32I 47 ops vs x86_64 thousands |
| 5 | Computer Architecture | Ch 5 | Instruction decoder + CPU integration + synthesize to Tang + first Virtus Console program | Petzold Ch 17 + Ch 18 | RV32I-Lite single-cycle vs ARMv8 OoO vs 6502 historical anchor |
| 6 | Assembler | Ch 6 | Two-pass tokenizer + pass-2 encoder + VOF emit + sum-to-N round-trip | Petzold Ch 17 + Ch 24 (dominant Petzold reading) | VOF v1 vs ELF vs Mach-O vs PE |
| 7 | Static Linker | Ch 6a | Symbol resolution + relocation + link + boot two files + corrupted-input handling | Petzold Ch 17 + Ch 22 + Ch 24 | Static linking vs dynamic linking (defer to CSA-201) |
| 8 | VM I (stack arithmetic + memory segments) | Ch 7 | Stack-arithmetic translator + memory-segment translator + end-to-end on silicon | Petzold Ch 17 + Ch 22 + Ch 24 | Stack VMs vs register VMs (JVM vs Dalvik vs WebAssembly) |
| 9 | VM II (program flow + function calls) | Ch 8 | Program-flow translator + function-call protocol + recursive factorial on silicon + gdb frame trace | Petzold Ch 17 + Ch 22 + Ch 25 (first Ch 25 citation) | Calling conventions: ARM AAPCS vs x86_64 System V vs RV32I-Lite Virtus |
| 10 | Compiler I (syntax analysis) | Ch 9 | Tokenizer + recursive-descent expression parser + full parser + round-trip | Petzold Ch 24 + Ch 25 | Recursive descent vs LR parsers (yacc/bison heritage) |
| 11 | Compiler II (code generation) | Ch 10 | Symbol-table builder + codegen + subroutines + end-to-end on silicon + Ghidra on your own compiler output | Petzold Ch 22 + Ch 24 (final) + Ch 25 (p. 382 milestone) | Treewalk codegen vs SSA-IR + register allocation (LLVM territory; defer) |
| 12 | Compiler III (OS-aware compilation) | Ch 11 | Library-call codegen + multi-file compilation + end-to-end on Virtus Console HDMI + compiler-output quality reconciliation | Petzold Ch 22 (final) + Ch 24 (final) + Ch 25 | Hosted vs freestanding C; calling into libc vs calling into Virtus OS stdlib |
| 13 | Virtus OS | Ch 12 | Implement Math + Memory/String/Array + Screen + Keyboard/Sound/VCP integration + capstone | Petzold Ch 22 (absolute final) + Ch 25 (absolute final, p. 382 last paragraph) | Virtus OS stdlib vs POSIX vs Win32 vs RTOS APIs |
| 14 | Capstone delivery + bridge | worksheets/ch12/csa-101-ladder-closes.md | Capstone integration + demo video + write-up + forward bridge to CSA-201 + CON-101 + RE-101 | Closing reflection on the full ladder | The bridge talk: where to take the skills next |
Anchor readings
Primary. Petzold CODE: The Hidden Language of Computer Hardware and Software, 1st edition (1999). Page numbers throughout the curriculum reference the 1st edition. The 2nd edition (2022) covers the same material with ±5-10 page shifts; locate by section title. Reading workload across the 14 weeks: ~60 pages from 6 Petzold chapters (Ch 4, 11, 17, 22, 24, 25). Full map: handouts/cross-chapter-petzold-reading-guide.md.
Secondary. Nisan and Schocken, The Elements of Computing Systems (the nand2tetris book). The course's hardware + toolchain structural model. Students who want a parallel reading should pair each CSA-101 chapter with the corresponding nand2tetris chapter.
Tertiary. Patterson and Hennessy, Computer Organization and Design RISC-V Edition. For students who want the full RV32I in detail; CSA-101 covers only the RV32I-Lite subset. Read in CSA-201, not CSA-101.
Per-week time budget
| Activity | Hours per week | Hours over 14 weeks |
|---|---|---|
| Lecture | ~3 hr | ~42 hr |
| Lab (hands-on with Tang or workbench) | ~5 hr | ~70 hr |
| Independent practice (Petzold reading + repo work + Toolchain Diary entries) | ~3 hr | ~42 hr |
| Total | ~11 hr/week | ~155 hr |
CSA-101 is the densest course in the academy at 155 hours. The middle weeks (5 through 12) are tighter than the edges; budget extra hours during Ch 5 silicon bring-up and Ch 12 OS integration.
Equipment
Canonical. Sipeed Tang Primer 25K FPGA development board (post-2026-05-01 ratification per Findings §22). GW5A-LV25 silicon with 22,800 LUT4 budget. Apicula toolchain target. ~$75 starter kit; ~$144 full kit including the Ch 11-12 standard-library labs. Order via Sipeed AliExpress shop or US distributors.
Tier-1 alternative. Sipeed Tang Nano 20K. GW2AR-LV18 Arora II silicon with 20,736 LUT4 budget. Apicula chipdb file GW2A-18C.msgpack.xz. Smaller form factor; advanced-track students who want a tighter hardware budget for parallel hand-modifications.
Browser-only path. No kit needed. The academy workbench at https://virtuscyberacademy.org/workbench/ provides the full Verilog → synthesis → place-and-route → bitstream pipeline in the browser. Stage 3 (bitstream emit) is server-hop via the academy-bitstream-server endpoint. Students using the browser path can do every lab except the final flash-to-silicon step; the capstone requires either a kit or instructor-arranged shared bench access.
Full equipment + install details: SETUP.md.
Toolchain Diary
CSA-101 introduces ~40 practitioner tools across the 14 weeks. Each lab worksheet names the tools it introduces. Students maintain a running toolchain-diary.md in their student repo per the template at worksheets/TEMPLATE-toolchain-diary.md. The pattern is canonical to Ch 4; every chapter from Ch 4 onward calls back to it. By Ch 12, students have a personal-reference document they will use years after the grade is posted.
Capstone (week 14)
The Virtus Console build. Your own RV32I-Lite CPU running on Tang Primer 25K silicon; your VCP integration; your Virtus OS program; your write-up. Full specification: CAPSTONE.md.
What feeds into CSA-101
Direct prerequisites: FND-101 (digital foundations) + FND-102 (Python and automation). HW-101 (hardware lab bench) is strongly recommended but not strictly required for the browser-path students.
What CSA-101 feeds
- CSA-201 picks up where Ch 12 ends. Full RV32I; MMU; PMP; driver track. The first course that assumes a working Tang Primer 25K bring-up.
- CON-101 uses the Ch 12 Virtus Console as the build target for a full retro-game development course. SNES-cousin controllers; sprite engine; audio engine; cartridge-format design.
- RE-101 uses the hardware-CPU instinct from CSA-101 Ch 5 + the bit-level encoding fluency from CSA-101 Ch 4 to reverse-engineer the Motorola SB6141 cable modem. See handouts/cross-chapter-sb6141-cousin-mapping-card.md for the cousin map.
Outline v0.1 prepared 2026-05-11. Updates after the first pilot cohort.