Sequential circuits. Four worksheets in worksheets/ch3/ take you from the D flip-flop (the smallest memory element) to byte-addressable RAM plus a precursor datapath that connects RAM, register file, and ALU.
Anchors the week
Week 3: Memory. Lab 3.4 (the precursor datapath) is the bridge from "you have an ALU" to "you almost have a CPU." Week 5 finishes the CPU by adding an instruction decoder; week 3 is the structural setup.
Concept the lab embodies
State across time. Combinational circuits compute outputs from inputs in the moment; sequential circuits hold state across clock cycles. The flip-flop is the boundary between the two paradigms. Metastability (lab 3.1) is the place where the clean digital abstraction meets the messy analog reality.
The four worksheets
| Worksheet | Time | Purpose |
|---|---|---|
| lab-3.1-d-flip-flop-metastability.md | ~90 min | The one time in the course you intentionally violate setup-and-hold timing |
| lab-3.2-register-file.md | ~90 min | Eight flip-flops + an address decoder |
| lab-3.3-byte-addressable-ram.md | ~90 min | Scale to a memory array |
| lab-3.4-precursor-datapath.md | ~120 min | ALU + register file + RAM = almost-a-CPU |
Grading rubric
Per-worksheet rubrics inline. Week-level: register-file and RAM simulate correctly; precursor datapath executes at least one hand-driven load/add/store sequence in simulation.
What's next
Lab pack 4: Machine Language. The bytes start to carry meaning.