Combinational circuits compute. Sequential circuits remember. By the end of the week you have built a D flip-flop, watched it go metastable on purpose, expanded it into a register file, expanded the register file into byte-addressable RAM, and wired the RAM into the precursor of a CPU's datapath.
Reading
- Chapter prose (primary). draft-chapters/ch3-memory-prose.md
- Petzold weave anchors. Ch 14 Feedback and Flip-Flops; Ch 16 Memory Memorabilia. ~33 pages, 1st edition. The cross-coupled NOR gates that hold a bit; the address-decoder structure that makes RAM addressable
- Cross-chapter handouts. None new
Lecture
lectures/ch3-memory-lecture.md. 3 hours. Key arc:
- Combinational vs sequential. The moment a circuit starts to depend on its own past output
- The latch (set-reset). The first memory element. Why it goes wrong (race conditions; metastability)
- The flip-flop. The clocked version that does not go wrong (under nominal timing)
- The register file. Eight flip-flops plus an address decoder
- Byte-addressable RAM. The same idea, scaled
Lab exercises
Five labs in worksheets/ch3/.
- lab-3.1-d-flip-flop-metastability.md, the metastability lab is a once-in-the-course thing. Do not skip.
- lab-3.2-register-file.md
- lab-3.3-byte-addressable-ram.md
- lab-3.4-precursor-datapath.md, this lab is the bridge from "you have an ALU and a register file" to "you almost have a CPU"
- lab-3.5-memory-map-explorer.md, Tier-1 companion: drive the Memory Map Explorer through 3 runtime scenarios and confirm the la-ptr-table at gp+0x40 (cross-references Ch 6a §6a.4 and Ch 7 §7.6)
Plan for ~6 hours of lab (the new Tier-1 explorer worksheet adds ~60 minutes on top of the original budget).
Independent practice
- Read Petzold Ch 14 + Ch 16 carefully. Notice that Petzold builds the same cross-coupled NOR latch before he gets to flip-flops
- Update your Toolchain Diary. Week 3 introduces: Verilog
always @(posedge clk), Verilator timing analysis, GTKWave clock waveform reading - Stretch: read the original 1965 Logic Design chapter on flip-flops by Hill and Peterson if you can find a library copy. The metastability problem was a real concern in early hardware
Where this RAM lives in the final memory map
You build a byte-addressable RAM this week. By Ch 12 the same RAM will hold the OS code, the application code, the VM segments, the stack, and the heap. The map below is the destination address space (drawn schematically, not to scale).
![Virtus Console 32-bit memory map. Ten regions ordered left-to-right by address: OS .text at 0x00000000, OS .data plus .bss at 0x00004000, Application .text at 0x00008000, the VM segment-base region at 0x00010000 highlighted amber, the stack at 0x00010030, the application heap at 0x00014000, and four peripheral windows at 0x80000000 through 0x80040000 (HDMI framebuffer, VCP shared memory, GPIO and GamePad, system control). An inset zoom expands the amber 0x00010000 to 0x00010030 region into 12 word-sized slots: LCL_addr, ARG_addr, THIS_addr, THAT_addr, then temp[0] through temp[7].](../../assets/diagrams/csa-101-memory-map-strip.svg)
Figure 3.1. The address space your RAM will eventually occupy. Today this is just "the thing you wired to your CPU's address bus"; by Ch 12 the same lines carry every region above. The amber block at 0x00010000 is the VM segment-base region introduced in Ch 7, drawn here so the Ch 3 reader sees where the eventual segments live. Cross-reference: cross-chapter-vm-segment-cheat-sheet.md.
Architecture comparison sidebar
RV32I-Lite has 8 registers; full RV32I has 32; x86_64 has 16 general-purpose plus 16 SSE/AVX. Each design point trades program-text density (more registers = less spilling = shorter code) against decoder complexity (more registers = wider register-select field in the instruction). RV32I-Lite's 8-register choice keeps the instruction encoding small enough to fit in the 32-bit word with room for opcodes.
Reflection prompts
- The flip-flop is the smallest memory element. The register file is 8 flip-flops with addressing. RAM is many flip-flops with more addressing. What does this tell you about the relationship between primitive and composite in computing?
- Why does the register file in your CPU live on-chip while the RAM lives off-chip? What changes about the engineering when memory moves further from the ALU?
- Metastability is a real physical phenomenon. What other physical phenomena does the CPU's logical abstraction try to hide from you, and what happens when the abstraction leaks?
What's next
Week 4 is the canonical voice template chapter. Machine language. The bytes carry meaning. You will hand-encode ten instructions and decode ten words. The bridge from "I built the hardware" to "I can speak to the hardware."