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Week 2: Boolean Arithmetic

523 words

Take the 4-bit ripple adder from Week 1 and scale it. By the end of the week you have a 32-bit ripple-carry adder, an adder-subtractor, a terminal ALU, and you have hand-encoded an IEEE-754 float and verified your encoding with a software floating-point adder.

Reading

  • Chapter prose (primary). draft-chapters/ch2-boolean-arithmetic-prose.md
  • Petzold weave anchors. Ch 12 A Binary Adding Machine, Ch 13 But What About Subtraction? (pp. 135-171, ~37 pages, 1st edition). Two's-complement as add-the-complement; the structural twin of the adder you build in lab
  • Cross-chapter handouts. None new this week; keep the Petzold reading guide bookmarked

Lecture

lectures/ch2-boolean-arithmetic-lecture.md. 3 hours. Key arc:

  • 4-bit to 32-bit. What changes; what stays the same
  • Two's complement: the algebraic trick that makes subtraction free
  • The adder-subtractor: one circuit, two operations, one select line
  • IEEE-754: how to encode a real number in 32 bits without losing your mind
  • The terminal ALU: adding logical operations (AND, OR, XOR) to the arithmetic ones

Lab exercises

Seven labs in worksheets/ch2/. The week's labs scale up the Week 1 adder.

Plan for ~6 hours of lab. Lab 2.4 (IEEE-754 hand encoding) is the most paper-and-pencil of any lab in the course; budget patience. Lab 2.6 is a Tier-1 calibration that pairs naturally with Lab 2.0's discrete-gate work and Lab 2.1's adder build.

Independent practice

  • Read Petzold Ch 12 + Ch 13 carefully. Notice that Petzold's 4-bit adder figure is structurally the same as yours from Week 1
  • Update your Toolchain Diary. Week 2 introduces: Verilog + operator behavior, Verilator simulation, GTKWave waveform inspection (or workbench equivalents)
  • Stretch: implement a 64-bit ripple adder by chaining two 32-bit adders. Notice why ripple carry stops scaling well

Architecture comparison sidebar

RV32I-Lite uses a single 32-bit ALU; x86_64 has a separate AGU (Address Generation Unit) for address arithmetic plus the main ALU; ARM NEON adds 128-bit SIMD lanes. Same building blocks; different packaging decisions. The "single ALU" choice is part of what makes RV32I-Lite buildable in a week.

Reflection prompts

  1. Two's complement turns subtraction into addition. What other "tricks" might let you turn one operation into another with a small piece of additional circuitry?
  2. The ripple-carry adder gets slower as it gets wider (each bit waits on the previous bit's carry). What might you do differently if you needed a fast 64-bit adder?
  3. IEEE-754 floating point trades precision for range. When would the trade be wrong?

What's next

Week 3 introduces memory. Combinational circuits (the ones you have built so far) compute outputs from inputs the moment the inputs change. Sequential circuits hold state across time. The flip-flop is the smallest of these.