Classroom Glossary Public page

Week 3: NES PPU and APU Internals

The NES PPU (picture processing unit) and APU (audio processing unit) are the chips that made the NES feel like the NES. This week you read the open-source community NES core's PPU and APU Verilog, modify the palette, and watch the change land on HDMI.


Reading

  • Altice, I Am Error, Chapter 3 (Famicom video and audio in deep detail). Critical reading; do not skip.
  • Copetti, NES writeup section on graphics + sound. Free.
  • nesdev.org wiki: PPU, the most-referenced PPU resource on the web.
  • Hugg, Designing Video Game Hardware in Verilog, the video-generation chapter. Hugg's approach is bottom-up; pair with the top-down community-core read.

Lecture

Roughly three hours across two sessions. Key arc:

  • PPU architecture. Tile-based background, sprite OAM, palette RAM, pattern tables.
  • The OAM (Object Attribute Memory) and how sprite-zero hit fires.
  • The APU. Two pulse channels, a triangle, a noise channel, a DMC sample. Why that mix.
  • Reading the community NES core's PPU module. Walk it on the projector.
  • Where the palette lives in HDL and how to flip it.

Lab pack

Lab Pack 3 modifies the NES palette and observes the change. See Lab Pack 3: NES Palette Modification.

Classroom tools

  • Workbench: Bitplane decomposer. Load any tile from a loaded ROM and walk the two planes pixel by pixel. R-2026-05-29n shipped the ROM-picker; use it on the NES core ROMs.
  • SPK-101 classroom: NES sprite inspector and APU inspector. Already-shipped tools that drop you into the same data the PPU outputs.
  • The community NES core source itself, mirrored in the academy student repo under cores/nes/.

Architecture comparison sidebar

The NES PPU is a fixed-function tile-and-sprite engine; the SNES PPU (you will see it in Module 6) is also tile-and-sprite but with Mode-7 and HDMA. Modern GPUs are general-purpose shaders. The retro-console pattern is a hardware engine that does the specific work the game needs and nothing else. The trade is silicon area against flexibility, the same trade you saw with the 6502 versus a general-purpose CPU.

Reflection prompts

  1. Why does the PPU have separate background and sprite address spaces? What does the separation buy?
  2. Read the community core's palette RAM module. How many palette entries are there and why?
  3. If you wanted to add a fifth APU channel, where in the HDL would you splice it in? What would you have to change in the mixer?

What is next

Module 4 picks up the mapper question. The NES cartridge had a small ROM space; the mapper chips let games carry more.