Classroom Public page

Week 6: Computer Architecture at the Block Level

1,233 words

Zoom out. The gates and flip-flops from weeks 3-5 organize into larger blocks: ALU, registers, memory, bus, control unit. A CPU is a connected set of these blocks. This week you see the whole machine.

Theme

You have built up from individual gates to adders to flip-flops to registers. This week you step back and look at the complete machine as a block diagram. The block diagram is the level at which architects and engineers communicate about computers: it hides the transistor details (which you already understand at a conceptual level) and exposes the information flow between components.

FND-101 covers the block level only. CSA-101 goes one level deeper: HDL, synthesis, and actual silicon. But understanding the block diagram is the prerequisite for understanding why CSA-101 exists.

Reading list (~1 hour)

  1. Petzold CODE, Ch 17 ("Automation"): putting together the complete machine; the role of the control unit
  2. Petzold CODE, Ch 18 ("From Abacuses to Chips"): historical path from mechanical to electronic computers; the block model emerges from this history
  3. Academy handout: handouts/cross-chapter-silicon-level-reading-guide.md (§6 Architecture Comparison Sidebar): the 6502, Z80, and RV32I-Lite block-level differences. Read as a forward pointer; you do not need to understand every term.

Lecture outline (~2 hours)

Section 1: The components of a CPU

A CPU has six major components at the block level:

  • ALU (Arithmetic Logic Unit): performs arithmetic (add, subtract) and logic (AND, OR, XOR) operations on operands. Produces a result and status flags (zero, carry, negative, overflow). This is the adder circuit from week 4, extended with logic operations and flag outputs.
  • Register file: the CPU's on-chip scratchpad. A bank of registers (each a set of flip-flops from week 5) that hold the values the CPU is currently working with. Fast; few in number (8-64 registers in typical designs); contents are lost when power is removed.
  • Program Counter (PC): one register with a special purpose: it holds the address of the next instruction to fetch from memory. After each instruction executes, the PC increments. A branch or jump instruction writes a new value to the PC.
  • Instruction Register (IR): holds the current instruction being decoded and executed. Fetched from memory into the IR; the control unit reads the IR to decide what to do.
  • Control unit: reads the instruction in the IR; generates the control signals that tell the ALU what operation to do, which registers to read/write, whether to access memory, and how to update the PC.
  • Memory interface: the connection between the CPU and external memory (RAM). Consists of an address bus (CPU sends an address), a data bus (data flows in or out), and a control bus (signals like read/write enable).

Section 2: Memory

  • RAM (Random Access Memory): stores the program's instructions and data while it runs
  • Address space: the range of addresses the CPU can reference. A 16-bit address bus can address 64 KB (2^16 bytes). A 32-bit address bus can address 4 GB.
  • Byte addressability: most modern CPUs address individual bytes. A 4-byte word at address 0x1000 occupies addresses 0x1000, 0x1001, 0x1002, 0x1003.
  • Read vs write: the CPU asserts a memory-read signal to load a value from RAM into a register; it asserts a memory-write signal to store a register value to RAM.

Section 3: The bus

  • A bus is a shared set of wires connecting multiple components. Simpler and cheaper than point-to-point wiring; the tradeoff is that only one component can use the bus at a time.
  • Three buses in a classic design:
    • Address bus: CPU drives the address; memory and I/O devices listen. Typically unidirectional (CPU to memory).
    • Data bus: bidirectional; carries data from memory to CPU (read) or from CPU to memory (write).
    • Control bus: timing and command signals (read/write, interrupt, bus grant, etc.)
  • Modern systems use more complex interconnect (PCI Express, AXI) but the address-data-control concept remains the same.

Section 4: I/O and memory-mapped I/O

  • Input/Output devices (keyboard, display, disk, network) are connected to the CPU's address and data buses
  • Memory-mapped I/O: devices appear in the address space as if they were memory locations. Write to address 0xFFF0 and a byte appears on the display; read from 0xFFF2 and you get the keyboard's current key state.
  • This is how the Virtus Peripheral IP Pack works in CSA-101: the Tang Primer 25K's HDMI and audio hardware appears to the RV32I-Lite CPU as memory-mapped registers.

Section 5: The block diagram as a communication tool

  • Engineers draw block diagrams when they want to reason about which component communicates with which, and over what interface
  • Each block has well-defined inputs and outputs; the block diagram hides the internal implementation
  • A chip designer thinks at the transistor level; a CPU architect thinks at the block level; a software developer thinks at the ISA level (instruction set); a programmer thinks at the language level. Each level is valid; each hides the one below it.
  • FND-101 teaches the block level. CSA-101 teaches the transistor-to-Verilog path. CSA-201 teaches ISA tradeoffs. Knowing all three makes you a much stronger engineer.

Labs (~90 minutes)

Lab 6.1: CPU Block Diagram (labs/lab-6-1-architecture-block-diagram.md)

  • Draw a complete CPU block diagram on paper (or in a free diagram tool like draw.io or Excalidraw)
  • Label: ALU, register file, PC, IR, control unit, address bus, data bus, data memory, instruction memory
  • For each connection, label what flows across it (instruction bytes, addresses, operands, control signals)
  • Artifact: photograph (paper diagram) or exported image (digital diagram) committed to Git

Independent practice (~4 hours)

  1. Read the block diagram section of the Wikipedia "Central processing unit" article; compare the generic block diagram to the one you drew in the lab
  2. Find a published block diagram of a real CPU (the 6502 or a modern ARM Cortex-M0 block diagram from the manufacturer's technical reference manual). Compare it to your diagram. What does it show that yours doesn't? What does yours show more clearly?
  3. Read handouts/cross-chapter-silicon-level-reading-guide.md §2 (the MOS 6502 die walkthrough). Try to identify, in the die description, where the ALU and register file are. You will not find a clean answer; that is the point.
  4. Consider: your laptop's CPU has billions of transistors but only a handful of registers (16 visible in x86_64). Where do all those transistors go if not in registers? Research "CPU cache" and add 3 sentences to your Toolchain Diary.

Reflection prompts (~30 minutes)

  1. You have seen computers at three levels this week: transistors, gates/flip-flops, and blocks. Which level feels most natural to you right now? Why?
  2. The bus connects many components but only one can use it at a time. What happens if two components try to use the bus simultaneously? (Guess; you will see the real answer in CSA-101.)
  3. Memory-mapped I/O means the keyboard and display look like memory to the CPU. Does this strike you as elegant, strange, or both? Why?
  4. The block diagram hides the transistor details. Is hiding details useful or dangerous? Give one example of each.
  5. After this week, how would you explain "what a computer is" to someone who has never thought about it?

What comes next

Week 7 puts the block diagram in motion: you trace a single instruction through the fetch-decode-execute cycle, step by step, watching the PC increment, the instruction register fill, the ALU compute, and the register file update. The blocks become a process.