Circuits that remember. A combinational circuit has no memory; change the inputs and the output changes instantly. A sequential circuit feeds its output back into its input, creating a stable state that persists until something deliberately changes it.
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The adder you studied last week has no state. Give it the same inputs twice in a row and it computes the same output both times; it has no notion of "last time." But a computer needs memory: it has to remember the result of a calculation, the current instruction, the address of the next instruction to fetch. All of that memory is built from circuits that feed output back into input.
This week you learn the SR latch (cross-coupled NAND or NOR gates), the D latch (transparent; output follows input while the enable signal is high), and the D flip-flop (clocked; output changes only on the clock edge). A D flip-flop is the universal memory primitive. An 8-bit register is 8 D flip-flops. A CPU's register file is a bank of registers.
Reading list (~1 hour)
- Petzold CODE, Ch 14 ("Feedback and Flip-Flops"): the R-S latch from relays; stabilizing feedback; the clock signal; the D flip-flop
- Wikipedia, "Flip-flop (electronics)" (SR latch section + D flip-flop section): complements Petzold with circuit diagrams
Lecture outline (~2 hours)
Section 1: Combinational vs sequential circuits
- Combinational: output is a pure function of current inputs. No memory, no clock needed.
- Sequential: output depends on current inputs AND on previous state. Requires feedback loops.
- A feedback loop routes the output of a circuit back to one of its inputs
- Stable states in feedback: the circuit settles into a state where input and output are self-consistent. Changing an external input forces a transition to a new stable state.
Section 2: The SR latch
- SR = Set-Reset; the simplest memory element
- Built from two cross-coupled NAND gates (or NOR gates; behavior differs slightly)
- With NAND gates: S=0 sets the output to 1; R=0 resets the output to 0; both S=R=1 is the "remember" (hold) state
- The "forbidden" state: S=R=0 simultaneously forces both outputs to 1, which is logically inconsistent; real circuits avoid this
- An SR latch stores one bit: whichever of Set or Reset was last asserted
Section 3: The D latch
- Problem with SR latch: the programmer must manage S and R separately. The D latch simplifies this.
- D latch inputs: D (data) and Enable (or Clock)
- When Enable=1: output Q follows input D (transparent mode)
- When Enable=0: output Q holds its last value (memory mode)
- D latches are used inside flip-flops and as hold elements in data paths
Section 4: The D flip-flop
- Problem with D latch: output changes continuously while Enable=1, which can cause timing problems
- D flip-flop: output changes only on the rising edge of the clock (or falling edge, depending on type)
- Master-slave construction: two D latches in series; first latch is transparent on low clock, second on high clock; output changes only at the low-to-high transition
- Setup and hold time: the D input must be stable for a minimum time before the clock edge (setup) and after it (hold); violating these causes metastability
- Practical importance: all synchronous digital design (every CPU, every register, every pipeline stage) is based on D flip-flops clocked by a common clock signal
Section 5: Registers and register files
- A register is N D flip-flops sharing a common clock and enable signal; together they store an N-bit value
- An 8-bit register: 8 flip-flops; holds one byte
- A register file: M registers with a shared read/write interface; an address decoder selects which register to read or write
- Your CSA-101 register file (x0-x7 in RV32I-Lite) is 8 registers x 32 bits = 256 flip-flops, all sharing the CPU's clock
- RAM is also built from latches or flip-flops at the cell level (SRAM) or from capacitors that need periodic refresh (DRAM); the distinction is speed vs density
Section 6: The clock signal
- The clock is a square wave: a signal that oscillates between 0 and 1 at a fixed frequency
- Modern CPUs run at 2-5 GHz: 2 to 5 billion clock edges per second
- Every flip-flop in the CPU (there are billions) updates its state on each relevant clock edge
- The clock frequency sets the throughput; the critical path (the slowest combinational logic between two flip-flops) sets the maximum clock frequency
Labs (~90 minutes)
Lab 5.1: Flip-Flop Signal Trace (labs/lab-5-1-flip-flop-trace.md)
- Given a timing diagram showing clock, D, and Q signals for a D flip-flop: mark the exact moment Q changes on each diagram
- Identify one setup-time violation in the diagram and explain why it causes incorrect behavior
- Artifact: annotated timing diagram + written explanation committed to Git
Independent practice (~4 hours)
- Draw an SR latch from scratch using two NAND gates and trace all four input combinations through it
- Verify De Morgan's law at the circuit level: show that a NOR-based SR latch and a NAND-based SR latch are equivalent when you account for the inverted-inputs convention
- Read Petzold Ch 14 again (the flip-flop section) and trace his relay-based latch step by step
- Look up "metastability in digital circuits." Summarize in 3 sentences what metastability is and why it is a practical concern in real designs
- How many D flip-flops does a 32-bit register require? How many does a 32-entry register file of 32-bit registers require? (These are the numbers for a full RV32I register file, the kind CSA-101 students build.)
Reflection prompts (~30 minutes)
- The feedback loop is what gives the SR latch its memory. In plain English, explain why feeding the output back to the input produces a stable stored state.
- The D flip-flop changes state only on the clock edge. Why does this constraint make digital design simpler and more reliable than if the flip-flop updated continuously?
- Setup time and hold time are physical constraints of the transistors in the flip-flop. If you build a circuit that violates setup time, the flip-flop may enter metastability. What does "metastability" mean in terms of the flip-flop's output?
- A CPU register file stores the values the CPU is currently working with. A hard drive (or SSD) stores persistent data. Both use flip-flops or equivalent at some level. What is the practical difference between "register" and "storage"?
- This week introduced the clock. Next week we add the program counter, the instruction register, and the ALU. At what level do those components use flip-flops?
What comes next
Week 6 zooms out to the block diagram. You have seen individual gates and flip-flops; now you see how they organize into the components a programmer thinks about: CPU, ALU, registers, memory, and the bus that connects them. You will draw the block diagram and label each component's role.