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Lab 6.1: CPU Block Diagram

578 words

~75 minutes. Draw a complete CPU block diagram, label every component, and annotate what flows across each connection.

Goal: produce a CPU block diagram with all major components labeled, all connections drawn, and all signals named. The diagram shows that you understand what each component does and how they communicate.

Estimated time: 75 minutes

Prerequisites: Week 6 lecture (ALU, register file, PC, IR, control unit, address bus, data bus, memory)

Tool choices

Draw on paper (photograph it for submission) or use a free digital tool:

  • draw.io at https://draw.io (best for precise diagrams; no login needed)
  • Excalidraw at https://excalidraw.com (freehand; easy to use)
  • Google Slides or PowerPoint (shapes + arrows; export as PNG)

Part A: Required components

Your diagram must include all of the following. Use labeled rectangles for each.

CPU boundary (draw a box around the CPU components to distinguish them from memory and I/O):

  • ALU (Arithmetic Logic Unit)
  • Register file (label it "Registers x0-x7" or similar)
  • Program Counter (PC)
  • Instruction Register (IR)
  • Control Unit

Outside the CPU:

  • Instruction Memory (or "ROM" for Harvard-architecture diagrams)
  • Data Memory (RAM)
  • I/O Device (label it "I/O / MMIO")

Part B: Required connections

Draw arrows between components for each of the following signals. Label each arrow with the signal name.

From To Signal label
PC Instruction Memory Address (to fetch next instruction)
Instruction Memory IR Instruction bytes
IR Control Unit Opcode + fields
Control Unit ALU ALU operation code (add? subtract? AND?)
Control Unit Register file Read/write enables + register numbers
Register file ALU Operand A, Operand B
ALU Register file Result
ALU Control Unit Flags (zero, carry, overflow)
Control Unit PC Next PC value (for jumps/branches)
ALU Data Memory Address (for load/store instructions)
Data Memory Register file Loaded data (for load instructions)
Register file Data Memory Data to store (for store instructions)

Part C: Labels and annotations

Add a short annotation (1 sentence) next to each component explaining its role. Example: "ALU: performs arithmetic (add, subtract) and logic (AND, OR, XOR) on two operands."

Part D: Two architectural questions

Write answers to these questions beneath or beside your diagram:

  1. Why are there two separate memory blocks (instruction memory and data memory) instead of one? What is the advantage of keeping them separate? (This is the Harvard vs von Neumann architecture distinction.)

  2. The control unit reads the IR and generates control signals. If you had to build the control unit, how would you implement it? (Hint: you already know a structure that maps input bit patterns to output bit patterns. What is it?)

Expected output / artifact

Submit either:

  • A photograph of a paper diagram + lab-6-1-answers.txt for Part D
  • A PNG/PDF export of a digital diagram + lab-6-1-answers.txt for Part D
git add lab-6-1/
git commit -m "lab-6-1: CPU block diagram + architectural questions"

Common pitfalls

  • Missing the IR: many first attempts omit the instruction register, connecting memory directly to the control unit. The IR is a real physical register that holds the current instruction while it decodes and executes.
  • Control unit connections: the control unit connects to almost every component. If your control unit has only 2 arrows, you probably missed some.
  • Flag path: the ALU produces flags (zero, carry) and the control unit reads them to decide whether a conditional branch is taken. This path is often forgotten.

Stretch (optional)

Look up the published block diagram of the MOS 6502 or a Cortex-M0 in ARM's technical reference manual. Compare one major difference to your diagram and note it in your answers file.

Lab 6.1 v0.1.