~75 minutes. Design a 1-bit half-adder by drawing the gate circuit and verifying its truth table. Extend to a full adder.
Goal: design a half-adder and a full adder on paper (or in a free drawing tool). Verify both circuits by filling in their truth tables from the gate structure.
Estimated time: 75 minutes
Prerequisites: Week 4 lecture (half-adder = XOR + AND; full adder = two half-adders + OR)
Part A: Half-adder circuit diagram
Draw a circuit diagram with:
- Two inputs labeled A and B
- One XOR gate: inputs A and B; output labeled Sum
- One AND gate: inputs A and B; output labeled Cout (carry-out)
You can draw this on paper (photograph it) or use a free web tool:
- draw.io at
https://draw.io(no login required; use the Extras > Edit Diagram mode with logic gate shapes) - Excalidraw at
https://excalidraw.com(freehand; use rectangle + label convention) - circuitverse.org at
https://circuitverse.org/simulator(has actual gate shapes)
Part B: Half-adder truth table
Fill in the truth table for your half-adder circuit. Derive each output from the gate definitions (not memory):
| A | B | Sum (A XOR B) | Cout (A AND B) |
|---|---|---|---|
| 0 | 0 | ||
| 0 | 1 | ||
| 1 | 0 | ||
| 1 | 1 |
Verify: when A=1 and B=1, Sum=0 and Cout=1. This represents "1+1=10 in binary" (two in decimal, requiring a carry).
Part C: Full adder circuit diagram
A full adder has three inputs (A, B, Cin) and two outputs (Sum, Cout). Draw the circuit:
- First half-adder: inputs A and B; outputs PartialSum (A XOR B) and PartialCarry1 (A AND B)
- Second half-adder: inputs PartialSum and Cin; outputs Sum (PartialSum XOR Cin) and PartialCarry2 (PartialSum AND Cin)
- OR gate: inputs PartialCarry1 and PartialCarry2; output Cout
Label all intermediate signals.
Part D: Full adder truth table
Fill in all 8 rows (3 inputs = 2^3 = 8 combinations):
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | ||
| 0 | 0 | 1 | ||
| 0 | 1 | 0 | ||
| 0 | 1 | 1 | ||
| 1 | 0 | 0 | ||
| 1 | 0 | 1 | ||
| 1 | 1 | 0 | ||
| 1 | 1 | 1 |
Verify: when A=1, B=1, Cin=1, Sum=1 and Cout=1 (representing 1+1+1=11 in binary = decimal 3).
Part E: 4-bit ripple-carry trace
Trace the addition 0101 + 0011 (5 + 3) through four full adders:
| Bit position | A | B | Cin | Sum | Cout |
|---|---|---|---|---|---|
| Bit 0 (rightmost) | 1 | 1 | 0 | ||
| Bit 1 | 0 | 1 | (Cout from bit 0) | ||
| Bit 2 | 1 | 0 | (Cout from bit 1) | ||
| Bit 3 | 0 | 0 | (Cout from bit 2) |
Write the 4-bit result: S3 S2 S1 S0 = ____. Convert to decimal. Verify: 5+3=8.
Expected output / artifact
lab-4-1-half-adder/:
circuit-half-adder.pngorcircuit-half-adder.jpg(your drawn circuit, photographed or exported)circuit-full-adder.pngorcircuit-full-adder.jpglab-4-1-worksheet.txtwith Parts B, D, and E truth tables filled in
git add lab-4-1/
git commit -m "lab-4-1: half-adder and full adder circuits + truth tables"
Common pitfalls
- Second half-adder's inputs: the second half-adder takes PartialSum (not A) as one input and Cin as the other. Drawing the diagram clearly prevents this confusion.
- Carry-out in Part E: each Cout feeds the next position's Cin. Be careful to carry from left to right (from bit 0 to bit 3 in the trace).
- Photograph lighting: if drawing on paper, take the photo near a window; phone cameras often produce unreadable images in dim light.
Stretch (optional)
Design a 4-bit ripple-carry adder that also performs subtraction: add a NOT gate on each B input and a carry-in toggle. How does setting Cin0=1 and inverting B implement two's complement subtraction?
Lab 4.1 v0.1.