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Lab 5.1: Flip-Flop Signal Trace

601 words

~60 minutes. Given timing diagrams for a D flip-flop, mark when the output Q changes and identify one setup-time violation.

Goal: read a timing diagram; mark the exact clock edge where Q updates; identify a setup-time violation by inspection.

Estimated time: 60 minutes

Prerequisites: Week 5 lecture (D flip-flop, setup time, hold time, clock edge)

Background

A rising-edge-triggered D flip-flop captures the value of D at the moment the clock (CLK) transitions from 0 to 1. The output Q updates immediately after that edge (after a small propagation delay, which we will ignore here). Between clock edges, Q holds its previous value regardless of what D does.

Setup time: D must be stable and correct for at least t_setup before the clock edge. If D changes too close to the clock edge, the flip-flop may capture the wrong value or enter metastability.

Part A: Trace 1 (no violations)

Given the following timing diagram, mark each rising clock edge with a vertical line, and mark the new value of Q that the flip-flop captures at each edge.

Time:  0  1  2  3  4  5  6  7  8
CLK:   0  1  0  1  0  1  0  1  0
D:     0  0  0  1  1  1  0  0  0
Q:     ?  ?  ?  ?  ?  ?  ?  ?  ?

Rising edges occur at times 1, 3, 5, 7 (where CLK goes from 0 to 1). At each rising edge, Q captures the current value of D.

Fill in Q for each time step. Remember: Q only changes at rising clock edges; between edges it holds the previous value. Q starts at 0.

Part B: Trace 2 (with a setup violation)

Assume the setup time is 1 time unit: D must be stable for at least 1 unit before the rising clock edge.

Time:  0  1  2  3  4  5  6  7  8
CLK:   0  1  0  1  0  1  0  1  0
D:     0  0  1  1  0  1  1  0  0
Q:     ?  ?  ?  ?  ?  ?  ?  ?  ?

Rising edges at times 1, 3, 5, 7. For each rising edge:

  1. What is D at the edge?
  2. Was D stable for at least 1 unit before the edge? (Check whether D changed at time edge-1.)
  3. If D changed at time edge-1 or edge itself, mark this as a setup violation.

Fill in Q normally where there is no violation. For a violation, mark Q as X (undefined/metastable).

Part C: Written analysis

Answer these questions in your worksheet:

  1. In Trace 1, how many times did Q change? At which time steps?
  2. In Trace 2, identify any setup violation you found. At what time did D change that caused the violation?
  3. In plain English: what does it mean for a flip-flop to "capture" a value? What physical process are we abstracting over?
  4. If you were designing a digital circuit and found a setup violation, what are two things you could do to fix it? (Hint: you can slow the clock, or change the circuit so D settles earlier.)

Expected output / artifact

lab-5-1-flip-flop-trace.txt with:

  • Filled Q sequences for Traces 1 and 2 (write out the full sequence: "Q: 0 0 0 0 1 1 1 0 0")
  • Identification of the setup violation in Trace 2
  • Answers to Part C
git add lab-5-1-flip-flop-trace.txt
git commit -m "lab-5-1: flip-flop timing trace"

Common pitfalls

  • Q changes between edges: it should not. If you wrote a Q value changing at a non-edge time, reread the flip-flop definition.
  • Which edge is rising: a rising edge is the 0-to-1 transition. At time 1, CLK goes from 0 (at time 0) to 1. At time 2, CLK goes from 1 to 0 (falling edge, not captured). Recheck your edge identification.
  • Setup violation at time 5 in Trace 2: look carefully at what D is doing at time 4 vs time 5.

Stretch (optional)

Draw your own timing diagram with a hold-time violation (D changes too soon after the rising clock edge, within t_hold). Describe what could go wrong when hold time is violated.

Lab 5.1 v0.1.