"The receiver designer's task is to recover the transmitted information from a signal that has been degraded by noise, interference, and the physical channel. Every component in the receiver chain contributes noise; the skill is in managing the cascade." — Wyglinski et al., Software-Defined Radio for Engineers, Ch 4
Lecture (90 min)
3.1 The Receiver Chain: A Cascade of Noise and Gain
A software-defined receiver is not a single component -- it is a cascade of stages, each with gain and noise figure. The received signal enters the antenna, traverses the cascade, and emerges as digital samples. Understanding what happens at each stage -- and how the noise accumulates -- is the Wyglinski receiver-chain budget framework.
The receive chain stages (RF to digital):
Antenna → LNA → BPF → Mixer (downconvert) → VGA → ADC → DSP
- LNA (Low Noise Amplifier): First active element after the antenna. Sets the system noise figure. A poorly designed LNA dominates the overall noise figure because noise from subsequent stages is divided by the LNA gain in the Friis formula.
- BPF (Bandpass Filter): Removes out-of-band signals that would create intermodulation products in the LNA and mixer. Critical for preventing receiver blocking and desensitization by strong adjacent-channel signals.
- Mixer: Downconverts the RF signal to an intermediate frequency (or directly to baseband in a direct-conversion / zero-IF receiver). Introduces noise and intermodulation products.
- VGA (Variable Gain Amplifier): Sets the signal level to optimally use the ADC's dynamic range. Too little gain: the signal uses only a few ADC bits (quantization noise dominates). Too much gain: the ADC clips (distortion).
- ADC: Converts the analog signal to digital samples. The ADC's effective number of bits (ENOB) and sample rate set the final digital bandwidth and noise floor.
- DSP: All subsequent processing is in software -- filtering, demodulation, decoding.
3.2 Friis Noise Figure Formula
The Friis formula is the fundamental tool for receiver chain noise budget:
F_total = F_1 + (F_2 - 1)/G_1 + (F_3 - 1)/(G_1·G_2) + ...
where F_i is the noise factor (linear, not dB) of stage i, G_i is the gain (linear) of stage i, and F_total is the overall receiver noise factor.
Key insight: The first stage (LNA) dominates. If G_1 is large (high LNA gain), subsequent stages' noise factors are divided by G_1 and become negligible. The LNA's noise figure is therefore the receiver system's noise figure in the limit of high LNA gain. This is why receiver designers obsess over the LNA's noise figure.
import numpy as np
def friis_noise_figure(NF_dB, G_dB):
"""
Compute cascaded noise figure using Friis formula.
NF_dB: list of noise figures in dB [stage1, stage2, ...]
G_dB: list of gains in dB [stage1, stage2, ...]
Returns: cascaded noise figure in dB
"""
# Convert to linear
F = [10**(nf/10) for nf in NF_dB] # noise factors
G = [10**(g/10) for g in G_dB] # gains (linear)
# Friis formula
F_total = F[0]
G_cumulative = G[0]
for i in range(1, len(F)):
F_total += (F[i] - 1) / G_cumulative
G_cumulative *= G[i]
return 10 * np.log10(F_total)
# Example: ANT-SDR E200 receive chain
# Stage: [LNA, BPF(loss), Mixer, VGA, ADC frontend]
NF_stages = [3.0, 2.0, 12.0, 8.0, 15.0] # noise figures in dB
G_stages = [15.0, -2.0, 0.0, 20.0, 0.0] # gains in dB (negative = loss)
NF_cascaded = friis_noise_figure(NF_stages, G_stages)
print(f"Cascaded noise figure: {NF_cascaded:.2f} dB")
# Sensitivity: minimum detectable signal
bandwidth_hz = 1e6 # 1 MHz channel
kT_dBm = -174.0 # thermal noise floor at 290 K in 1 Hz, dBm/Hz
SNR_min_dB = 10.0 # minimum SNR for demodulation (depends on modulation)
sensitivity_dBm = kT_dBm + 10*np.log10(bandwidth_hz) + NF_cascaded + SNR_min_dB
print(f"Receiver sensitivity: {sensitivity_dBm:.1f} dBm")
print(f"(At {bandwidth_hz/1e6:.0f} MHz BW, {SNR_min_dB:.0f} dB SNR_min)")
System sensitivity is the minimum detectable signal power at the antenna:
P_min [dBm] = kT₀ + 10·log₁₀(B) + NF_total + SNR_min
= -174 + 10·log₁₀(B_Hz) + NF + SNR_min
For a 1 MHz channel, 5 dB noise figure, 10 dB SNR minimum: P_min = -174 + 60 + 5 + 10 = -99 dBm.
3.3 Dynamic Range: IP3 and the Spurious-Free Dynamic Range
The noise floor sets the bottom of the dynamic range. The top is set by the onset of nonlinear distortion -- specifically, the third-order intermodulation (IM3) products.
Third-order intercept point (IP3): When two large tones at f_1 and f_2 enter a nonlinear amplifier, intermodulation products appear at 2f_1 - f_2 and 2f_2 - f_1 (among others). The IM3 products grow as the cube of the input amplitude. The IIP3 (input-referred third-order intercept) is the fictitious input power at which the IM3 product would equal the fundamental -- an extrapolated intersection point (the receiver compresses before reaching it).
For a receive chain, the IIP3 is:
IIP3_total [dBm] ≈ IIP3_first - G_1 [dB] (approximately -- limited by first stage)
The spurious-free dynamic range (SFDR) is:
SFDR [dB] = (2/3) · (IIP3 - P_noise_floor)
This is the range of input signal powers over which the receiver operates without significant distortion. For an LNA with IIP3 = 10 dBm and a noise floor of -100 dBm: SFDR = (2/3) · 110 = 73 dB.
def sfdr(IIP3_dBm, noise_floor_dBm):
"""Spurious-free dynamic range in dB."""
return (2/3) * (IIP3_dBm - noise_floor_dBm)
IIP3 = 10.0 # dBm
P_noise = -99.0 # dBm (from sensitivity example)
print(f"SFDR: {sfdr(IIP3, P_noise):.1f} dB")
3.4 ADC Dynamic Range and ENOB
The ADC quantizes the analog signal to a digital representation. An ideal N-bit ADC has a dynamic range of 6.02N + 1.76 dB (the SQNR for a full-scale sinusoid). But real ADCs have non-ideal behavior: differential nonlinearity (DNL), integral nonlinearity (INL), aperture jitter, and thermal noise reduce the effective number of bits (ENOB) below the nominal bit count.
ADC requirement from system spec:
Required ADC dynamic range = SFDR + some margin
Required ENOB ≈ (SFDR [dB] - 1.76) / 6.02
For SFDR = 73 dB: ENOB ≈ (73 - 1.76)/6.02 ≈ 11.8 bits. A 12-bit or 14-bit ADC would be appropriate.
The ANT-SDR E200's AD9361 uses a 12-bit ADC. At full dynamic range, this provides ~72 dB SNDR -- adequate for most SDR work, tight for high-dynamic-range receive scenarios.
3.5 Full-Duplex Architecture: Simultaneous Transmit and Receive
A half-duplex radio takes turns transmitting and receiving on the same frequency. A full-duplex radio transmits and receives simultaneously on the same frequency -- which requires the transmitted signal (potentially 30 dBm) to not overwhelm the receiver (sensitivity ~-100 dBm at 1 MHz). The self-interference cancellation problem: cancel a signal that is 130 dB stronger than the desired received signal.
Self-interference cancellation layers:
- Antenna isolation: Directional antennas, physical separation, cross-polarization; achieves 20-40 dB
- Analog cancellation: A cancellation signal fed from the transmit chain to the receive chain with adjustable delay and amplitude; achieves 30-40 dB
- Digital cancellation: After ADC, subtract a digital replica of the self-interference; achieves 20-40 dB
Combined: 70-120 dB cancellation -- sufficient to approach full-duplex on software-defined hardware.
Full-duplex on the ANT-SDR E200: The AD9361 supports a 2×2 MIMO configuration with two separate receive and transmit RF paths. True simultaneous full-duplex requires the above cancellation architecture; a common lab demonstration uses two adjacent frequency bands (simulated full-duplex) or digital loopback.
3.6 Architecture Comparison Sidebar: SDR Receiver Architectures
Three dominant receive architectures in the software-defined radio ecosystem, each with a different location for the IF-to-baseband conversion:
| Architecture | IF stage | Conversion | Strengths | Weaknesses |
|---|---|---|---|---|
| Superheterodyne | Fixed IF (e.g., 70 MHz) | Analog IF → baseband | Mature; high performance; excellent selectivity | Complex; many analog components; fixed BW |
| Direct conversion (zero-IF) | None | RF direct to baseband | Simple; integrates well in CMOS (AD9361 model) | DC offset, I/Q imbalance, LO leakage; flicker noise |
| Direct sampling | None | RF sampled directly by high-speed ADC | Flexible; fewer analog stages | ADC must sample at full RF frequency; expensive; very high bandwidth |
The ANT-SDR E200 and most SDR hardware (RTL-SDR, HackRF, USRP B200) use direct conversion (zero-IF). The I/Q imbalance and DC offset artifacts are real: the DC spike visible in SDR waterfall displays at f_LO is the LO leakage artifact of the direct-conversion mixer. Software correction of I/Q imbalance is a common SDR post-processing step.
3.7 Anchor Weave: Wyglinski et al. Ch 4-5
Wyglinski et al. SDR for Engineers Chapters 4 (Receiver Architectures) and 5 (Transmitter Architectures) are the primary anchors for this week. Chapter 4 develops the Friis cascade, the dynamic range constraints, and the three receiver architectures in the same order as this lecture -- the lecture is designed to be read alongside Ch 4. Chapter 5 addresses the transmit chain: the power amplifier's nonlinearity, predistortion, and the spectrum-shaping role of the transmit filter.
The central Wyglinski argument at RF-301 register: The design of a software-defined receiver is a chain of budget decisions. Noise figure budget. Dynamic range budget. ADC bit budget. Power budget. Each budget constraint propagates to the next stage. Understanding how to compute and allocate each budget is what distinguishes a receiver designer from a receiver user. Belt-5 students leave RF-301 as receiver designers.
Lab Introduction
Lab 3 (20 pts): Full-duplex software-defined receiver chain on ANT-SDR E200; SNR budget measured across the chain. See labs/lab-3.md.
Independent Practice
- Wyglinski Ch 4: work through the Friis cascade example in §4.2; verify with Python using the
friis_noise_figure()function above - Compute the minimum detectable signal for your RTL-SDR dongle: look up its noise figure (typically 6-10 dB depending on LNA); use a 1 MHz channel and 12 dB SNR minimum
- Explain in 2-3 sentences why a superheterodyne receiver has better image rejection than a direct-conversion receiver at the same channel bandwidth
- What limits the SFDR of the RTL-SDR's RTL2832U chipset? (Hint: check the datasheet for ADC bit depth and IP3 estimates)