Assumes a working CSA-101 environment (Tang Primer 25K flashed, riscv32-unknown-elf toolchain installed, Verilator or iverilog working). This guide adds the DE10-Nano toolchain and the software tools specific to CSA-201.
Hardware setup
Tang Primer 25K (carry-over from CSA-101)
Your CSA-101 board is your starting point. Keep the CSA-101 bitstream on it as a reference. You will synthesize new bitstreams starting in Module 1 as you widen the register file and add the M extension. The Tang Primer 25K's 20,736 LUT4 capacity is enough for Modules 1-8 (estimated cumulative ~13K LUT4 through the MMU).
Flash tool: openFPGALoader --board tangnano20k or the Gowin programmer GUI. The yowasp browser path at the academy workbench Tab 3 supports pre-flash sanity checks without installing Gowin EDA locally.
DE10-Nano (new in CSA-201)
The DE10-Nano (Terasic) hosts a Cyclone V 5CSEBA6U23I7 FPGA (41,910 ALMs; ~85K equivalent LUT4). It also carries 1 GB DDR3 SDRAM, an SD card slot, USB-Blaster II JTAG, HDMI output, and the DE10-Nano I/O board GPIO connector. This is the production-scale capstone target: Virtus OS v2 runs on the DE10-Nano from Module 7 onward.
Purchase. Order from Terasic directly (terasic.com) or authorized distributors (~$130 at time of writing). The academy maintains a hardware-platform page with current pricing; see the link in the course landing.
Initial board test. Flash the Terasic factory demo bitstream first (included on the factory SD card) to verify the board is functional before you modify it.
Pi 4 station kit
The Pi 4 serves as a development workstation and cross-compilation host for modules where your laptop is not available. Minimum: Raspberry Pi 4 4 GB, USB-C 5V 3A power supply, HDMI cable, 16 GB microSD, USB keyboard.
Software setup
Quartus Prime Lite 23.1+
Required for DE10-Nano bitstream synthesis (Cyclone V is an Altera/Intel device; open-source nextpnr does not support Cyclone V). Download from intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime.html.
- Download the Lite edition installer for Linux x86_64 or Windows (no license needed for Cyclone V Lite).
- Install to
/opt/quartus(Linux) orC:\intelFPGA_lite\23.1(Windows). Add<install>/quartus/binto PATH. - Install the Cyclone V device pack when prompted.
- Verify:
quartus_sh --versionreturnsVersion 23.1.x.
SignalTap II Logic Analyzer. Built into Quartus; used for Modules 7 and 12 to probe signals inside the FPGA during runtime. No additional install required.
RISC-V toolchain (should already be installed from CSA-101)
Verify: riscv32-unknown-elf-gcc --version. The CSA-201 labs use -march=rv32im (adds M extension) and -march=rv32ima_zicsr (adds CSR instructions). If your installed toolchain predates M-extension support, rebuild with --with-arch=rv32im.
Prebuilt binaries. The SiFive Freedom Tools release at github.com/sifive/freedom-tools/releases includes riscv32-unknown-elf-gcc with full RV32IM_Zicsr support. Extract to /opt/riscv32.
Verilator + iverilog (should already be installed from CSA-101)
Verify: verilator --version (expect 5.x or later). CSA-201 uses Verilator for the Sv32 MMU testbench (Module 7) and the privilege-mode trap testbench (Module 2). iverilog remains available for quick waveform dumps.
riscv-tests
The official RISC-V compliance test suite. Used in Modules 1 and 2 to verify full RV32I instruction coverage.
git clone https://github.com/riscv-software-src/riscv-tests.git
cd riscv-tests
git submodule update --init --recursive
./configure --prefix=/opt/riscv-tests
make
make install
The compiled test binaries live at /opt/riscv-tests/share/riscv-tests/isa/. Relevant suites for CSA-201: rv32ui-p-* (user-level integer), rv32um-p-* (M extension), rv32mi-p-* (machine-level trap handling).
Sail RISC-V (Module 2 onward, optional but recommended)
Sail is the official formal model of the RISC-V ISA. Used to generate a golden reference trace to compare against your Verilator sim. Install: opam install sail (OCaml package manager) or use the pre-built binary release from github.com/riscv/sail-riscv/releases.
Verify: sail -help prints usage.
QEMU RISC-V (Modules 2 and 7)
QEMU with the RISC-V target is useful for testing privilege-mode software before you have hardware. Install on Debian/Ubuntu:
sudo apt-get install qemu-system-riscv32
Verify: qemu-system-riscv32 --version.
gdb-multiarch + OpenOCD (Module 12 onward)
For source-level debugging on DE10-Nano via JTAG:
sudo apt-get install gdb-multiarch openocd
OpenOCD config for DE10-Nano USB-Blaster II: openocd -f interface/altera-usb-blaster2.cfg -f target/cyclone5.cfg.
godbolt.org (Module 6)
No installation. The Compiler Explorer runs in a browser at godbolt.org. Lab 6.1 uses the C source pane with target RISC-V rv32gc gcc 14.1, flags -O0, -O2, -O3. No account needed for read-only use; create a free account to save and share permalinks.
Reference implementation
The vca-csa-201 support repo lives at ../virtus-academy-support/vca-csa-201/. It contains:
hdl/core/-- the growing HDL for each F-dispatch (csrfile.v, regfile.v, muldiv.v, privilege.v, trap_ctrl.v, pmp.v, mmu.v, tlb.v, ptw.v, ...)sim/-- Verilator and cocotb testbenchesfirmware/-- Virtus OS v2 kernel and bootloader sourcetests/-- riscv-tests integration harness
Check that repo's STATUS.md before Module 1 to see which F-dispatches are sim-certified. The support repo is instructor-facing; students work from the lab scaffolds provided per-week, not the reference directly.
Toolchain Diary setup (carry-over from CSA-101)
CSA-201 adds ~30 new tools to the diary. Open your Toolchain Diary now and prepare entries for the tools you will encounter this term:
Quartus Prime Lite, SignalTap II, Verilator (advanced use), iverilog (continued), Sail RISC-V, riscv-tests, riscv-formal, godbolt.org (Compiler Explorer), perf (Linux), OpenSBI, U-Boot RISC-V, Linux 6.x RISC-V, BusyBox, gdb-multiarch, JTAG/OpenOCD, QEMU RISC-V, spike (RISC-V ISA simulator), device-tree compiler (dtc), objdump -d on RV32IM binaries, readelf on ELF headers, nm (symbol table), addr2line, valgrind (for host-side compiler dev), Wireshark (Module 13: ENC28J60 packet capture).
You do not need all of these before the first lab. Add entries as you encounter each tool.