Virtual Tang Primer 25K
CSA-101 §11.7 + CSA-102 Weeks 1-4. 2D render of the Sipeed Tang Primer 25K + Dock, driven by the same 6502 emulator the §11.8 REPL uses. Bitstream-load animation; 8 GPIO LEDs; 8 input buttons; UART pane. CSA-101 catalog.
How to use this
Pick a demo bitstream from the dropdown (each one is a pre-assembled 6502 program targeting the board's memory-mapped IO).
Click Load bitstream to play the load animation; click Run to start the emulator. The 8
LEDs across the top of the board reflect the byte at $D013; the UART console shows whatever the program writes
to $D012; the 8 buttons across the bottom let you click input, which the program reads from
$D014.
This is the no-hardware path for the CSA-101 Week 8 lab. The real Tang Primer 25K shows the same LED pattern from the same bitstream; the only difference is the synthesis toolchain runs locally for the physical board (per the Week 8 lab writeup) instead of being pre-canned on the academy's side. The board IO contract here matches the real board's pin map, so a program written for this surface runs unchanged on the physical board.
Board Tang Primer 25K + Dock (silkscreen + LEDs + buttons + UART jack + HDMI)
UART console writes to $D012 land here
CPU state A / X / Y / PC / cycles + LED byte
$D013):0b00000000Buttons click to press; reads as 1 at $D014
.fs bitstream upload (Yosys + nextpnr + gowin_pack
output) is the same drop-and-flash UX path, with a Verilog interpreter substituted for the pre-canned program loader.
The VirtusLang Workbench (Tab 3) already ships Yosys + nextpnr + Gowin synthesis to
a real .fs file in-browser; the seam here is the binding layer that runs the bitstream against this board's
pin map.